FPGA-Based Storage Reference Design Doubles NAND Flash Life
via Circuit Cellar
Altera Corp. recently developed a storage reference design based on its Arria 10 SoCs that doubles the life of NAND flash. In addition, can increase the number of program-erase cycles by up to 7×. The design features an Arria 10 SoC with an integrated dual-core ARM Cortex A9 processor in an optimized, single-chip solution. It uses a Mobiveil SSD controller and NVMdurance NAND optimization software. This reference design provides improved performance and flexibility in NAND utilization while reducing the cost of the NAND array by increasing the lifetime of data center equipment.
Mobiveil’s controller supports multi-core architectures, enabling threads to run on each core with their own queue and interrupt without any locks required. NVMdurance’s NAND flash optimization software monitors the NAND Flash’s condition and automatically adjusts the control parameters in real time. The reference design also features end-to-end data protection, encryption and compression, and optimizes throughput and power consumption, all in a small silicon footprint.
Altera’s NAND storage reference design is available today.